The present invention relates generally to the field of memory cell arrangement, and more particularly to testing a memory cell arrangement.
Typically, designers of modern memory cell arrangements (e.g., in Central Processing Unit (CPU) caches, main memories, etc.) aim to ensure that memory arrangement meets high performance criteria. One way to ensure that memory arrangements meet the high performance criteria is to identify malfunctions and provide accurate corrective actions. In some instances, malfunctions can be caused by a plurality of test conditions.